Understanding How the New Intel® HyperFlexTM FPGA Architecture Enables Next- Generation High-Performance Systems

To address the ever increasing bandwidth requirements of next-generation high-performance systems, FPGA vendors are continually making incremental improvements in their device architectures. Even with these advanced architectures, designers often resort to implementing their designs using very wide on-chip buses. In fact, on-chip buses of 512, 1,024 or 2,048 bits wide are increasingly common. Although this method improves data throughput in the FPGA core, these wide buses consume significant fabric resources and power. Also, as the FPGA fills up, routing resources can become congested and the core clock frequency may be limited.